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Nepomnyashchiy, O. V.
Ryjenko, I. V.
Shaydurov, V. V.
Sirotinina, N. Y.
Postnikov, A. I.
2019-07-01T07:21:33Z
2019-07-01T07:21:33Z
2017-12
Nepomnyashchiy, O. V. The VLSI high-level synthesis for building onboard spacecraft control systems [Текст] / O. V. Nepomnyashchiy, I. V. Ryjenko, V. V. Shaydurov, N. Y. Sirotinina, A. I. Postnikov // Proceedings of the Scientific-Practical Conference "Research and Development - 2016. — 2017. — С. 229-238
https://elib.sfu-kras.ru/handle/2311/69570
https://elib.sfu-kras.ru/handle/2311/110464
Текст статьи не публикуется в открытом доступе в соответствии с политикой журнала.
Using small spacecrafts for a wide range of research and applied purposes is one of the major trends in the aerospace field. Modular-network architectures implemented on the "system-on-chip" hardware platform provide required characteristics of onboard control systems. Selecting this system architecture significantly increases demands on very large scale integration (VLSI) design efficiency and project solution quality. In this paper, we propose a new approach to VLSI high-level synthesis based on a functional-flow parallel computing model. The modified VLSI design flow uses a functional-flow parallel programming language Pythagoras, which allows describing a VLSI operation algorithm with the maximal degree of parallelism. An offered intermediate representation of VLSI architecture in form of a control flow graph and a data flow graph provides an opportunity for synthesizing circuits and verifying projects on the stage of a formal description, without returning to previous hierarchical levels of the project. A set of software tools supporting new design process is developed. The proposed technology is successfully tested on the example of a digital signal processing function. Further, this technology is suggested for use in the synthesis of onboard control system components for small spacecrafts.
small spacecraft
control systems
parallel computing
data flow
functional programming
integrated circuit
algorithm
formal verification
high-level synthesis
The VLSI high-level synthesis for building onboard spacecraft control systems
Journal Article
Journal Article Preprint
229-238
50.51
2019-07-01T07:21:33Z
10.1007/978-3-319-62870-7_25
Институт космических и информационных технологий
Кафедра вычислительной техники
Proceedings of the Scientific-Practical Conference "Research and Development - 2016
без квартиля


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