Methods and Algorithms for a High-Level Synthesis of the Very-Large-Scale Integration
URI (for links/citations):http://elib.sfu-kras.ru/handle/2311/27843
Институт космических и информационных технологий
Кафедра вычислительной техники
Journal Name:WSEAS TRANSACTIONS on COMPUTERS
Journal Quartile in Scopus:Q3
Bibliographic Citation:Nepomnyashchy, Oleg. Methods and Algorithms for a High-Level Synthesis of the Very-Large-Scale Integration [Текст] / Oleg Nepomnyashchy, Alexandr Legalov, Valery Tyapkin, Igor Ryzhenko, Vladimir Shaydurov // WSEAS TRANSACTIONS on COMPUTERS. — 2016. — Т. 15. — С. 239-247
We develop methods and algorithms for a high-level synthesis and a formal verification of the architecture for very-large-scale integration (VLSI). The proposed approach is based on the functional-flow paradigm of parallel computing and enables one to perform architecture-independent VLSI synthesis by the construction of a computing model in the form of intermediate structures of control and data graphs. This approach also provides an opportunity to verify a design at the formal description stage before the synthesis of the register-gate representation. Algorithms and methods are developed for the construction and optimization of an intermediate representation of a computing model, the verification, and going to the register-gate description of VLSI. The stages of the high-level VLSI synthesis are formed in the context of the proposed technique. An example of the synthesis of a typical module is considered for a digital signal processing. Results of the practical modeling are presented for an example.